1. Field of the Invention
The present invention relates to an A/D converter which transforms multi-channel analog signals into digital data.
2. Description of the Prior Art
An A/D converter of this type is disclosed in Data Book AD7581 published by Analog Devices Inc. FIG. 1 shows the arrangement of this A/D converter, which is arranged to be connected to a CPU such as microcomputer. The A/D converter includes an 8-channel multiplexer 1, an A/D converting circuit 2 which converts one of the analog input signals selected by the multiplexer 1 into an 8-bit digital data byte, a dual-port RAM 3 which temporarily stores the 8-bit data byte, a CPU 4, an interface control logic circuit 5 which selects the channel of the multiplexer 1 and addresses the dual-port RAM 3, and a priority arbitration circuit 6 which selects a signal with the higher order precedence out of the write signal and read signal when both signals arise simultaneously.
The operation of the above A/D converter is as follows. Eight analog signals are received by the 8-channel multiplexer 1, and the interface control logic circuit 5 operates on the multiplexer 1 to pass selectively one of the analog signals to the A/D converting circuit 2. The analog signals at the inputs of the multiplexer 1 are fed to the A/D converting circuit sequentially by being scanned from channel 7 to channel 0 at a certain interval, and resultant digital data are stored in predetermined address locations in the dual-port RAM 3.
After A/D conversion for the signal of channel 0 has completed, the next cycle of A/D converting operation begins with channel 7 in response to the signal indicating that the last data has been stored in the dual-port RAM 3. The operation goes on automatically following the clock signal applied to the circuit 5.
The CPU 4 makes access to an address location in the dual-port RAM 3 so that it fetches digital data of the corresponding channel.
FIG. 2 shows the above operation in a timing chart, in which the A/D conversion start signal common for all channels is shown at (a), and the A/D conversion end signal is shown at (b). Time interval t shown at (c) represents the time needed to convert an analog signal into digital data. The time lag, which is the time interval from the starting of A/D conversion to the entry of digital data in the CPU, is expressed as a sum of the conversion time and a time interval from the end of conversion to the read-out of digital data in the RAM by the CPU. The time lag T is shown at (e) for the case, as an example, when the CPU reads out data of channel 6 at a time point shown by (d).
In the conventional system, in which the data read-out operation of the CPU and the state of A/D conversion are in asynchronism with each other, the amount of time lag from A/D conversion to read-out is indeterminate for every channel. For input analog signals which should have a minimum time lag between detection and read-out because of the need to respond to fast varying or crucial signals, such conventional system is unsatisfactory for control purposes because of the variation in time lag, especially when the delay between detection and read-out is substantially increased.
In order to overcome the above problem, it is conceivable that the CPU is placed in an interrupt mode in response to a status signal indicating the end of A/D conversion and the CPU fetches digital data in this mode. This method is effective for minimizing the time lag to an amount substantially equal to the A/D conversion time for all channels, but has an adverse effect that the frequent interrupt operations deteriorate the CPU's processing ability for the main control purpose.